This invention relates to field effect transistors and more particularly to power metal oxide semiconductor field-effect transistor (MOSFET) having improved device edge termination characteristics.
Power electronic applications typically employ a power metal-oxide-semiconductor field effect transistor (MOSFET). Power MOSFETs are desired to sustain a relatively high breakdown voltage, while having a desirable low on-resistance. Typically, power MOSFET devices are formed from a clustered array of transistors fabricated on a substrate referred to as an active area.
Surrounding the active area is a region into which electric fields produced in the active area distribute. This is referred to as a termination area. It is desirable to maximize the breakdown voltage of the power MOSFET, a in the termination region beyond that of the active cell region. If termination breakdown voltage is lower than that of active region, the avalanche current will crowd into termination region and result in lower avalanche capability. In most applications, highest possible avalanche current is most desired.
In a conventional Shielded Gate Transistor (SGT) MOSFET, the termination region design is most challenging since the last active cell trench, which borders the termination region, behaves differently compared with the ones inside of the active region.
There is a need, therefore, to provide suitable termination region design to maximize the breakdown voltage of the power MOSFET.
A semi conductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate. The semiconductor device includes an active area having a plurality of active transistors each of which has source, drain and gate regions. The source and gate regions are spaced-apart and are electrically insulated from each other. The termination area surrounds the active area. The termination area includes a plurality of spaced-apart termination trenches, each filled with an electrically conductive material and an electrically insulative material. The electrically insulative material is disposed between the electrically conductive material and the conductive material of the substrate. One of the plurality of termination trenches is disposed between the active area and the remaining trenches of the plurality of termination trenches, in which a gate region is formed in superimposition and spaced-apart with a shielded gate region such that a cross-sectional area of the gate poly is less than a cross-sectional area of the gate region in a transistor forming an asymmetric gate. Also disclosed is a method for forming the semiconductor device. These and other embodiments are discussed more fully below.